diff options
| author |   Chris Zankel <czankel@tensilica.com> | 2005-06-23 22:01:26 -0700 |
|---|---|---|
| committer |   Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-06-24 00:05:22 -0700 |
| commit | 9a8fd5589902153a134111ed7a40f9cca1f83254 (patch) | |
| tree | 6f7a06de25bdf0b2d94623794c2cbbc66b5a77f6 /include/asm-xtensa/cache.h | |
| parent | [PATCH] xtensa: Architecture support for Tensilica Xtensa Part 5 (diff) | |
| download | linux-dev-9a8fd5589902153a134111ed7a40f9cca1f83254.tar.xz linux-dev-9a8fd5589902153a134111ed7a40f9cca1f83254.zip | |
[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 6
The attached patches provides part 6 of an architecture implementation for the
Tensilica Xtensa CPU series.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-xtensa/cache.h')
| -rw-r--r-- | include/asm-xtensa/cache.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/include/asm-xtensa/cache.h b/include/asm-xtensa/cache.h new file mode 100644 index 000000000000..5aae3f12407c --- /dev/null +++ b/include/asm-xtensa/cache.h @@ -0,0 +1,32 @@ +/* + * include/asm-xtensa/cacheflush.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * 2 of the License, or (at your option) any later version. + * + * (C) 2001 - 2005 Tensilica Inc. + */ + +#ifndef _XTENSA_CACHE_H +#define _XTENSA_CACHE_H + +#include <xtensa/config/core.h> + +#if XCHAL_ICACHE_SIZE > 0 +# if (XCHAL_ICACHE_SIZE % (XCHAL_ICACHE_LINESIZE*XCHAL_ICACHE_WAYS*4)) != 0 +# error cache configuration outside expected/supported range! +# endif +#endif + +#if XCHAL_DCACHE_SIZE > 0 +# if (XCHAL_DCACHE_SIZE % (XCHAL_DCACHE_LINESIZE*XCHAL_DCACHE_WAYS*4)) != 0 +# error cache configuration outside expected/supported range! +# endif +#endif + +#define L1_CACHE_SHIFT XCHAL_CACHE_LINEWIDTH_MAX +#define L1_CACHE_BYTES XCHAL_CACHE_LINESIZE_MAX + +#endif /* _XTENSA_CACHE_H */ |