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| author |   Dave Airlie <airlied@redhat.com> | 2020-07-02 15:17:31 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2020-07-02 15:17:31 +1000 |
| commit | 9555152beb1143c85c03f9b9de59863cbbe89f4b (patch) | |
| tree | 3d43b98bf373e72fe84562adafe3bcbb45d21054 /include/drm | |
| parent | Merge tag 'drm-misc-next-2020-06-26' of git://anongit.freedesktop.org/drm/drm-misc into drm-next (diff) | |
| parent | drm/amd/powerplay: Fix NULL dereference in lock_bus() on Vega20 w/o RAS (diff) | |
| download | linux-dev-9555152beb1143c85c03f9b9de59863cbbe89f4b.tar.xz linux-dev-9555152beb1143c85c03f9b9de59863cbbe89f4b.zip | |
Merge tag 'amd-drm-next-5.9-2020-07-01' of git://people.freedesktop.org/~agd5f/linux into drm-next
amd-drm-next-5.9-2020-07-01:
amdgpu:
- DC DMUB updates
- HDCP fixes
- Thermal interrupt fixes
- Add initial support for Sienna Cichlid GPU
- Add support for unique id on Arcturus
- Major swSMU code cleanup
- Skip BAR resizing if the bios already did id
- Fixes for DCN bandwidth calculations
- Runtime PM reference count fixes
- Add initial UVD support for SI
- Add support for ASSR on eDP links
- Lots of misc fixes and cleanups
- Enable runtime PM on vega10 boards that support BACO
- RAS fixes
- SR-IOV fixes
- Use IP discovery table on renoir
- DC stream synchronization fixes
amdkfd:
- Track SDMA usage per process
- Fix GCC10 compiler warnings
- Locking fix
radeon:
- Default to on chip GART for AGP boards on all arches
- Runtime PM reference count fixes
UAPI:
- Update comments to clarify MTYPE
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200701155041.1102829-1-alexander.deucher@amd.com
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'include/drm')
| -rw-r--r-- | include/drm/amd_asic_type.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h index b1230e33d506..0c5bd1134460 100644 --- a/include/drm/amd_asic_type.h +++ b/include/drm/amd_asic_type.h @@ -54,6 +54,7 @@ enum amd_asic_type { CHIP_NAVI10, /* 25 */ CHIP_NAVI14, /* 26 */ CHIP_NAVI12, /* 27 */ + CHIP_SIENNA_CICHLID, /* 28 */ CHIP_LAST, }; |