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| author |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2022-06-29 12:52:04 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-08-31 18:13:53 -0700 |
| commit | 7e5073a74f60a3197773fa57b796a59ae40e6542 (patch) | |
| tree | d5333a4c0c06671ddb011a57ed3335c5412c2720 /include/dt-bindings/reset | |
| parent | clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent (diff) | |
| download | linux-dev-7e5073a74f60a3197773fa57b796a59ae40e6542.tar.xz linux-dev-7e5073a74f60a3197773fa57b796a59ae40e6542.zip | |
dt-bindings: reset: mt8195: Add resets for PCIE controllers
Add the reset index for PCIe P0 and P1 (PCIe0, PCIe1) on MT8195.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220629105205.173471-2-angelogioacchino.delregno@collabora.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings/reset')
| -rw-r--r-- | include/dt-bindings/reset/mt8195-resets.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h index 0b1937f14b36..39d6bcce745b 100644 --- a/include/dt-bindings/reset/mt8195-resets.h +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -31,5 +31,7 @@ #define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0 #define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1 #define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2 +#define MT8195_INFRA_RST2_PCIE_P0_SWRST 3 +#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ |