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| author |   Peter De Schrijver <pdeschrijver@nvidia.com> | 2017-02-23 12:44:39 +0200 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2017-03-20 14:04:45 +0100 |
| commit | 34ac2c278b306cc3006dd5cbfaff4ec52065bf6f (patch) | |
| tree | 1cac5e108c4f0c050fa796ed682777126beab16c /include/dt-bindings | |
| parent | clk: tegra: Fix pll_a1 iddq register, add pll_a1 (diff) | |
| download | linux-dev-34ac2c278b306cc3006dd5cbfaff4ec52065bf6f.tar.xz linux-dev-34ac2c278b306cc3006dd5cbfaff4ec52065bf6f.zip | |
clk: tegra: Fix ISP clock modelling
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model
this as 1 mux/divider clock and child gate clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/tegra210-car.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 35288b20f2c9..f5c6563ab2d6 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -39,7 +39,7 @@ /* 20 (register bit affects vi and vi_sensor) */ /* 21 */ #define TEGRA210_CLK_USBD 22 -#define TEGRA210_CLK_ISP 23 +#define TEGRA210_CLK_ISPA 23 /* 24 */ /* 25 */ #define TEGRA210_CLK_DISP2 26 @@ -349,7 +349,7 @@ #define TEGRA210_CLK_PLL_RE_OUT1 319 /* 320 */ /* 321 */ -/* 322 */ +#define TEGRA210_CLK_ISP 322 /* 323 */ /* 324 */ /* 325 */ |