diff options
| author |   David S. Miller <davem@davemloft.net> | 2021-09-21 10:58:36 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-09-21 10:58:36 +0100 |
| commit | 6a3807536328c632ead28911b7524bf14cfe71aa (patch) | |
| tree | 8e67db0e1a8a0bdbb90f1fd0ec35e9e28559d126 /include/linux/brcmphy.h | |
| parent | net/ipv4/syncookies.c: remove superfluous header files from syncookies.c (diff) | |
| parent | net: dsa: bcm_sf2: Request APD, DLL disable and IDDQ-SR (diff) | |
| download | linux-dev-6a3807536328c632ead28911b7524bf14cfe71aa.tar.xz linux-dev-6a3807536328c632ead28911b7524bf14cfe71aa.zip | |
Merge branch 'iddq-sr-mode'
Florian Fainelli says:
====================
net: phy: broadcom: IDDQ-SR mode
This patch series adds support for the IDDQ with soft recovery mode
which allows power savings of roughly 150mW compared to a simple
BMCR.PDOWN power off (called standby power down in Broadcom datasheets).
In order to leverage these modes we add a new PHY driver flags for
drivers to opt-in for that behavior, the PHY driver is modified to do
the appropriate programming and the PHYs on which this was tested get
updated to have an appropriate suspend/resume set of functions.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/brcmphy.h')
| -rw-r--r-- | include/linux/brcmphy.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h index 07e1dfadbbdf..b119d6819d6c 100644 --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h @@ -67,6 +67,7 @@ #define PHY_BRCM_CLEAR_RGMII_MODE 0x00000004 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00000008 #define PHY_BRCM_EN_MASTER_MODE 0x00000010 +#define PHY_BRCM_IDDQ_SUSPEND 0x000000220 /* Broadcom BCM7xxx specific workarounds */ #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff) @@ -84,6 +85,7 @@ #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ +#define MII_BCM54XX_EXP_SEL_TOP 0x0d00 /* TOP_MISC expansion register select */ #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ #define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */ @@ -243,6 +245,12 @@ #define MII_BCM54XX_EXP_EXP97 0x0f97 #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c +/* Top-MISC expansion registers */ +#define BCM54XX_TOP_MISC_IDDQ_CTRL (MII_BCM54XX_EXP_SEL_TOP + 0x06) +#define BCM54XX_TOP_MISC_IDDQ_LP (1 << 0) +#define BCM54XX_TOP_MISC_IDDQ_SD (1 << 2) +#define BCM54XX_TOP_MISC_IDDQ_SR (1 << 3) + /* * BCM5482: Secondary SerDes registers */ |