diff options
| author |   Florian Fainelli <f.fainelli@gmail.com> | 2016-11-22 11:40:55 -0800 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2016-11-24 15:45:53 -0500 |
| commit | d06f78c4232d6a84b50839f61d9d7fbb222d8118 (patch) | |
| tree | 9301f4e9cd2bee1e719d2acfce8a679e05b7e521 /include/linux/brcmphy.h | |
| parent | net: phy: broadcom: Move bcm54xx_auxctl_{read, write} to common library (diff) | |
| download | linux-dev-d06f78c4232d6a84b50839f61d9d7fbb222d8118.tar.xz linux-dev-d06f78c4232d6a84b50839f61d9d7fbb222d8118.zip | |
net: phy: broadcom: Add support code for downshift/Wirespeed
Broadcom's Wirespeed feature allows us to configure how auto-negotiation
should behave with fewer working pairs of wires on a cable. Add support
code for retrieving and setting such downshift counters using the
recently added ethtool downshift tunables.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/brcmphy.h')
| -rw-r--r-- | include/linux/brcmphy.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h index 848dc508ef57..f9f8aaf9c943 100644 --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h @@ -114,6 +114,7 @@ #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007 #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8) +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN (1 << 4) #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007 @@ -130,6 +131,7 @@ #define BCM_LED_SRC_INTR 0x6 #define BCM_LED_SRC_QUALITY 0x7 #define BCM_LED_SRC_RCVLED 0x8 +#define BCM_LED_SRC_WIRESPEED 0x9 #define BCM_LED_SRC_MULTICOLOR1 0xa #define BCM_LED_SRC_OPENSHORT 0xb #define BCM_LED_SRC_OFF 0xe /* Tied high */ @@ -141,6 +143,14 @@ * Shadow values go into bits [14:10] of register 0x1c to select a shadow * register to access. */ + +/* 00100: Reserved control register 2 */ +#define BCM54XX_SHD_SCR2 0x04 +#define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100 +#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2 +#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2 +#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7 + /* 00101: Spare Control Register 3 */ #define BCM54XX_SHD_SCR3 0x05 #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001 |