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| author |   Dave Jiang <dave.jiang@intel.com> | 2020-05-13 11:47:49 -0700 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2020-06-17 19:45:14 +0530 |
| commit | 47ec7f09bc107720905c96bc37771e4ed1ff0aed (patch) | |
| tree | d0d500633ad1d51812bc8ed04394e16859bc296c /include/linux/dmaengine.h | |
| parent | dmaengine: mmp_tdma: share the IRQ line (diff) | |
| download | linux-dev-47ec7f09bc107720905c96bc37771e4ed1ff0aed.tar.xz linux-dev-47ec7f09bc107720905c96bc37771e4ed1ff0aed.zip | |
dmaengine: cookie bypass for out of order completion
The cookie tracking in dmaengine expects all submissions completed in
order. Some DMA devices like Intel DSA can complete submissions out of
order, especially if configured with a work queue sharing multiple DMA
engines. Add a status DMA_OUT_OF_ORDER that tx_status can be returned for
those DMA devices. The user should use callbacks to track the completion
rather than the DMA cookie. This would address the issue of dmatest
complaining that descriptors are "busy" when the cookie count goes
backwards due to out of order completion. Add DMA_COMPLETION_NO_ORDER
DMA capability to allow the driver to flag the device's ability to complete
operations out of order.
Reported-by: Swathi Kovvuri <swathi.kovvuri@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Tested-by: Swathi Kovvuri <swathi.kovvuri@intel.com>
Link: https://lore.kernel.org/r/158939557151.20335.12404113976045569870.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'include/linux/dmaengine.h')
| -rw-r--r-- | include/linux/dmaengine.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index e1c03339918f..9f9a13a2c01f 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -39,6 +39,7 @@ enum dma_status { DMA_IN_PROGRESS, DMA_PAUSED, DMA_ERROR, + DMA_OUT_OF_ORDER, }; /** @@ -61,6 +62,7 @@ enum dma_transaction_type { DMA_SLAVE, DMA_CYCLIC, DMA_INTERLEAVE, + DMA_COMPLETION_NO_ORDER, /* last transaction type for creation of the capabilities mask */ DMA_TX_TYPE_END, }; |