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| author |   David Woodhouse <David.Woodhouse@intel.com> | 2015-09-09 11:58:59 +0100 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2015-10-15 11:24:45 +0100 |
| commit | ae853ddb9ad5e7c01cad3fbf016040acd961f407 (patch) | |
| tree | 7d48a76f8849125e95dcddc5b29937317537abd5 /include/linux/intel-iommu.h | |
| parent | iommu/vt-d: Fix ATSR handling for Root-Complex integrated endpoints (diff) | |
| download | linux-dev-ae853ddb9ad5e7c01cad3fbf016040acd961f407.tar.xz linux-dev-ae853ddb9ad5e7c01cad3fbf016040acd961f407.zip | |
iommu/vt-d: Introduce intel_iommu=pasid28, and pasid_enabled() macro
As long as we use an identity mapping to work around the worst of the
hardware bugs which caused us to defeature it and change the definition
of the capability bit, we *can* use PASID support on the devices which
advertised it in bit 28 of the Extended Capability Register.
Allow people to do so with 'intel_iommu=pasid28' on the command line.
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'include/linux/intel-iommu.h')
| -rw-r--r-- | include/linux/intel-iommu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 08802b99f057..1d69c1d3aa9a 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -121,7 +121,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) #define ecap_srs(e) ((e >> 31) & 0x1) #define ecap_ers(e) ((e >> 30) & 0x1) #define ecap_prs(e) ((e >> 29) & 0x1) -/* PASID support used to be on bit 28 */ +#define ecap_broken_pasid(e) ((e >> 28) & 0x1) #define ecap_dis(e) ((e >> 27) & 0x1) #define ecap_nest(e) ((e >> 26) & 0x1) #define ecap_mts(e) ((e >> 25) & 0x1) |