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| author |   Shanker Donthineni <shankerd@codeaurora.org> | 2018-03-21 20:58:49 -0500 |
|---|---|---|
| committer |   Marc Zyngier <marc.zyngier@arm.com> | 2018-03-23 09:24:25 +0000 |
| commit | 6eb486b66a3094cdcd68dc39c9df3a29d6a51dd5 (patch) | |
| tree | 95e04c50da1d0477c2ce6a23ebe63ea4c4c8b139 /include/linux/irqchip/arm-gic-v3.h | |
| parent | irqchip: Add a driver for the Microsemi Ocelot controller (diff) | |
| download | linux-dev-6eb486b66a3094cdcd68dc39c9df3a29d6a51dd5.tar.xz linux-dev-6eb486b66a3094cdcd68dc39c9df3a29d6a51dd5.zip | |
irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling
Booting with GICR_CTLR.EnableLPI=1 is usually a bad idea, and may
result in subtle memory corruption. Detecting this is thus pretty
important.
On detecting that LPIs are still enabled, we taint the kernel (because
we're not sure of anything anymore), and try to disable LPIs. This can
fail, as implementations are allowed to implement GICR_CTLR.EnableLPI
as a one-way enable, meaning the redistributors cannot be reprogrammed
with new tables.
Should this happen, we fail probing the redistributor and warn the user
that things are pretty dire.
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
[maz: reworded changelog, minor comment and message changes]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'include/linux/irqchip/arm-gic-v3.h')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 9aacea2aa938..5988473e4abf 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -106,6 +106,7 @@ #define GICR_PIDR2 GICD_PIDR2 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) +#define GICR_CTLR_RWP (1UL << 3) #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) |