diff options
| author |   Zenghui Yu <yuzenghui@huawei.com> | 2020-06-30 21:41:26 +0800 |
|---|---|---|
| committer |   Marc Zyngier <maz@kernel.org> | 2020-07-27 08:55:03 +0100 |
| commit | 6d4c4479f80141a2a24ac798a86942b1225206df (patch) | |
| tree | 74867f68b955444ad4dd91358b2630ffe52b4372 /include/linux/irqchip | |
| parent | irqchip/qcom-pdc: Allow QCOM_PDC to be loadable as a permanent module (diff) | |
| download | linux-dev-6d4c4479f80141a2a24ac798a86942b1225206df.tar.xz linux-dev-6d4c4479f80141a2a24ac798a86942b1225206df.zip | |
irqchip/gic-v3: Remove unused register definition
[maz: The GICv3 spec has evolved quite a bit since the draft the Linux
driver was written against, and some register definitions are simply gone]
As per the GICv3 specification, GIC{D,R}_SEIR are not assigned and the
locations (0x0068) are actually Reserved. GICR_MOV{LPI,ALL}R are two IMP
DEF registers and might be defined by some specific micro-architecture.
As they're not used anywhere in the kernel, just drop all of them.
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
[maz: added context explaination]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200630134126.880-1-yuzenghui@huawei.com
Diffstat (limited to 'include/linux/irqchip')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 6c36b6cc3edf..f6d092fdb93d 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -19,7 +19,6 @@ #define GICD_CLRSPI_NSR 0x0048 #define GICD_SETSPI_SR 0x0050 #define GICD_CLRSPI_SR 0x0058 -#define GICD_SEIR 0x0068 #define GICD_IGROUPR 0x0080 #define GICD_ISENABLER 0x0100 #define GICD_ICENABLER 0x0180 @@ -119,14 +118,11 @@ #define GICR_WAKER 0x0014 #define GICR_SETLPIR 0x0040 #define GICR_CLRLPIR 0x0048 -#define GICR_SEIR GICD_SEIR #define GICR_PROPBASER 0x0070 #define GICR_PENDBASER 0x0078 #define GICR_INVLPIR 0x00A0 #define GICR_INVALLR 0x00B0 #define GICR_SYNCR 0x00C0 -#define GICR_MOVLPIR 0x0100 -#define GICR_MOVALLR 0x0110 #define GICR_IDREGS GICD_IDREGS #define GICR_PIDR2 GICD_PIDR2 |