diff options
| author |   Catalin Marinas <catalin.marinas@arm.com> | 2014-07-24 14:14:42 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2014-07-25 13:12:15 +0100 |
| commit | 72c5839515260dce966cd24f54436e6583288e6c (patch) | |
| tree | f6a65a5899490397eaa8c6a609452d365f05273d /include/linux/irqchip | |
| parent | Merge tag 'deps-irqchip-gic-3.17' of git://git.infradead.org/users/jcooper/linux (diff) | |
| download | linux-dev-72c5839515260dce966cd24f54436e6583288e6c.tar.xz linux-dev-72c5839515260dce966cd24f54436e6583288e6c.zip | |
arm64: gicv3: Allow GICv3 compilation with older binutils
GICv3 introduces new system registers accessible with the full msr/mrs
syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent
binutils understand the new syntax. This patch introduces msr_s/mrs_s
assembly macros which generate the equivalent instructions above and
converts the existing GICv3 code (both drivers/irqchip/ and
arch/arm64/kernel/).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Olof Johansson <olof@lixom.net>
Tested-by: Olof Johansson <olof@lixom.net>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'include/linux/irqchip')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 42 |
1 files changed, 22 insertions, 20 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 30cb7556d43f..03a4ea37ba86 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -18,6 +18,8 @@ #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H #define __LINUX_IRQCHIP_ARM_GIC_V3_H +#include <asm/sysreg.h> + /* * Distributor registers. We assume we're running non-secure, with ARE * being set. Secure-only and non-ARE registers are not described. @@ -125,17 +127,17 @@ #define ICH_VMCR_PMR_SHIFT 24 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) -#define ICC_EOIR1_EL1 S3_0_C12_C12_1 -#define ICC_IAR1_EL1 S3_0_C12_C12_0 -#define ICC_SGI1R_EL1 S3_0_C12_C11_5 -#define ICC_PMR_EL1 S3_0_C4_C6_0 -#define ICC_CTLR_EL1 S3_0_C12_C12_4 -#define ICC_SRE_EL1 S3_0_C12_C12_5 -#define ICC_GRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) +#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) +#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) +#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) +#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) +#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) +#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) #define ICC_IAR1_EL1_SPURIOUS 0x3ff -#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) #define ICC_SRE_EL2_SRE (1 << 0) #define ICC_SRE_EL2_ENABLE (1 << 3) @@ -143,16 +145,16 @@ /* * System register definitions */ -#define ICH_VSEIR_EL2 S3_4_C12_C9_4 -#define ICH_HCR_EL2 S3_4_C12_C11_0 -#define ICH_VTR_EL2 S3_4_C12_C11_1 -#define ICH_MISR_EL2 S3_4_C12_C11_2 -#define ICH_EISR_EL2 S3_4_C12_C11_3 -#define ICH_ELSR_EL2 S3_4_C12_C11_5 -#define ICH_VMCR_EL2 S3_4_C12_C11_7 +#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) +#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) +#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) +#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) +#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) +#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5) +#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) -#define __LR0_EL2(x) S3_4_C12_C12_ ## x -#define __LR8_EL2(x) S3_4_C12_C13_ ## x +#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x) +#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x) #define ICH_LR0_EL2 __LR0_EL2(0) #define ICH_LR1_EL2 __LR0_EL2(1) @@ -171,13 +173,13 @@ #define ICH_LR14_EL2 __LR8_EL2(6) #define ICH_LR15_EL2 __LR8_EL2(7) -#define __AP0Rx_EL2(x) S3_4_C12_C8_ ## x +#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) #define ICH_AP0R0_EL2 __AP0Rx_EL2(0) #define ICH_AP0R1_EL2 __AP0Rx_EL2(1) #define ICH_AP0R2_EL2 __AP0Rx_EL2(2) #define ICH_AP0R3_EL2 __AP0Rx_EL2(3) -#define __AP1Rx_EL2(x) S3_4_C12_C9_ ## x +#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) #define ICH_AP1R0_EL2 __AP1Rx_EL2(0) #define ICH_AP1R1_EL2 __AP1Rx_EL2(1) #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) @@ -189,7 +191,7 @@ static inline void gic_write_eoir(u64 irq) { - asm volatile("msr " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq)); + asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq)); isb(); } |