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| author |   Ben Widawsky <ben.widawsky@intel.com> | 2022-01-23 16:29:10 -0800 |
|---|---|---|
| committer |   Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:28 -0800 |
| commit | 303ebc1b1741b6a18349d8e5753c2d25fdb41a21 (patch) | |
| tree | 25c8a89c652a2fef648efc8fbfddb2d20ccbd291 /include/linux/mfd/git:/ssh:/git@git.zx2c4.com | |
| parent | cxl/pci: Add new DVSEC definitions (diff) | |
| download | linux-dev-303ebc1b1741b6a18349d8e5753c2d25fdb41a21.tar.xz linux-dev-303ebc1b1741b6a18349d8e5753c2d25fdb41a21.zip | |
cxl/acpi: Map component registers for Root Ports
This implements the TODO in cxl_acpi for mapping component registers.
cxl_acpi becomes the second consumer of CXL register block enumeration
(cxl_pci being the first). Moving the functionality to cxl_core allows
both of these drivers to use the functionality. Equally importantly it
allows cxl_core to use the functionality in the future.
CXL 2.0 root ports are similar to CXL 2.0 Downstream Ports with the main
distinction being they're a part of the CXL 2.0 host bridge. While
mapping their component registers is not immediately useful for the CXL
drivers, the movement of register block enumeration into core is a vital
step towards HDM decoder programming.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
[djbw: fix cxl_regmap_to_base() failure cases]
Link: https://lore.kernel.org/r/164298415080.3018233.14694957480228676592.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include/linux/mfd/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions