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| author |   Dan Williams <dan.j.williams@intel.com> | 2022-01-23 16:32:01 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:33 -0800 |
| commit | c1915142e8c1168498c8b08cd4e02728d1c33563 (patch) | |
| tree | bec52ff5ee6a7ac5241587ac282d3d1808a9d8bb /include/linux/mfd/git:/ssh:/git@git.zx2c4.com | |
| parent | tools/testing/cxl: Fix root port to host bridge assignment (diff) | |
| download | linux-dev-c1915142e8c1168498c8b08cd4e02728d1c33563.tar.xz linux-dev-c1915142e8c1168498c8b08cd4e02728d1c33563.zip | |
tools/testing/cxl: Mock one level of switches
The CXL port enumeration process adds intermediate CXL ports that are
discovered between "root" CXL ports enumerated by 'cxl_acpi' and
endpoints enumerated by 'cxl_pci + cxl_mem'. Test the dynamic discovery
of intermediate switch ports in a CXL topology.
Link: https://lore.kernel.org/r/164298432189.3018233.13142151550113000967.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include/linux/mfd/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions