diff options
| author |   Michael Srba <Michael.Srba@seznam.cz> | 2020-11-10 14:00:47 +0100 |
|---|---|---|
| committer |   Lee Jones <lee.jones@linaro.org> | 2020-11-19 08:34:23 +0000 |
| commit | 4556fe8f16e0225f5df7a57d123e0d55717bf2aa (patch) | |
| tree | 560de8630cf4ae9efbdecc296b3f1be047bdd291 /include/linux/mfd/rt5033-private.h | |
| parent | dt-binding: mfd: syscon: add Rockchip QoS register compatibles (diff) | |
| download | linux-dev-4556fe8f16e0225f5df7a57d123e0d55717bf2aa.tar.xz linux-dev-4556fe8f16e0225f5df7a57d123e0d55717bf2aa.zip | |
mfd: rt5033: Fix errorneous defines
Fix regulators on rt5033 by converting some values to bitmasks which were
errorneously not defined as such in the header file.
Cc: Beomho Seo <beomho.seo@samsung.com>
Fixes: 0b271258544b ("mfd: rt5033: Add Richtek RT5033 driver core.")
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'include/linux/mfd/rt5033-private.h')
| -rw-r--r-- | include/linux/mfd/rt5033-private.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/include/linux/mfd/rt5033-private.h b/include/linux/mfd/rt5033-private.h index f812105c538c..2d1895c3efbf 100644 --- a/include/linux/mfd/rt5033-private.h +++ b/include/linux/mfd/rt5033-private.h @@ -91,14 +91,14 @@ enum rt5033_reg { #define RT5033_RT_HZ_MASK 0x01 /* RT5033 control register */ -#define RT5033_CTRL_FCCM_BUCK_MASK 0x00 -#define RT5033_CTRL_BUCKOMS_MASK 0x01 -#define RT5033_CTRL_LDOOMS_MASK 0x02 -#define RT5033_CTRL_SLDOOMS_MASK 0x03 -#define RT5033_CTRL_EN_BUCK_MASK 0x04 -#define RT5033_CTRL_EN_LDO_MASK 0x05 -#define RT5033_CTRL_EN_SAFE_LDO_MASK 0x06 -#define RT5033_CTRL_LDO_SLEEP_MASK 0x07 +#define RT5033_CTRL_FCCM_BUCK_MASK BIT(0) +#define RT5033_CTRL_BUCKOMS_MASK BIT(1) +#define RT5033_CTRL_LDOOMS_MASK BIT(2) +#define RT5033_CTRL_SLDOOMS_MASK BIT(3) +#define RT5033_CTRL_EN_BUCK_MASK BIT(4) +#define RT5033_CTRL_EN_LDO_MASK BIT(5) +#define RT5033_CTRL_EN_SAFE_LDO_MASK BIT(6) +#define RT5033_CTRL_LDO_SLEEP_MASK BIT(7) /* RT5033 BUCK control register */ #define RT5033_BUCK_CTRL_MASK 0x1f @@ -247,11 +247,11 @@ enum rt5033_fuel_reg { #define RT5033_FUEL_BAT_PRESENT 0x02 /* RT5033 PMIC interrupts */ -#define RT5033_PMIC_IRQ_BUCKOCP 2 -#define RT5033_PMIC_IRQ_BUCKLV 3 -#define RT5033_PMIC_IRQ_SAFELDOLV 4 -#define RT5033_PMIC_IRQ_LDOLV 5 -#define RT5033_PMIC_IRQ_OT 6 -#define RT5033_PMIC_IRQ_VDDA_UV 7 +#define RT5033_PMIC_IRQ_BUCKOCP BIT(2) +#define RT5033_PMIC_IRQ_BUCKLV BIT(3) +#define RT5033_PMIC_IRQ_SAFELDOLV BIT(4) +#define RT5033_PMIC_IRQ_LDOLV BIT(5) +#define RT5033_PMIC_IRQ_OT BIT(6) +#define RT5033_PMIC_IRQ_VDDA_UV BIT(7) #endif /* __RT5033_PRIVATE_H__ */ |