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authorWei WANG <wei_wang@realsil.com.cn>2013-08-21 09:46:25 +0800
committerSamuel Ortiz <sameo@linux.intel.com>2013-08-30 14:24:07 +0200
commit84d72f9cc21d6e41c620dd34b8248734cd02d995 (patch)
treef84a291737af9885fb573adc4844fc4e0c0c74c5 /include/linux/mfd/rtsx_pci.h
parentMerge tag 'mfd-lee-3.12-1' of git://git.linaro.org/people/ljones/mfd (diff)
downloadlinux-dev-84d72f9cc21d6e41c620dd34b8248734cd02d995.tar.xz
linux-dev-84d72f9cc21d6e41c620dd34b8248734cd02d995.zip
mfd: mmc: rtsx: Change default tx phase
The default phase can meet most cards' requirement, but it is not the optimal one. In some extreme situation, the rx phase point produced by the following tuning process will drift quite a distance. Before tuning UHS card, this patch will set a more proper initial tx phase point, which is calculated from statistic data, and can achieve a much better tx signal quality. Signed-off-by: Wei WANG <wei_wang@realsil.com.cn> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Chris Ball <cjb@laptop.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'include/linux/mfd/rtsx_pci.h')
-rw-r--r--include/linux/mfd/rtsx_pci.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index daefca1bafb3..d1382dfbeff0 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -847,6 +847,9 @@ struct rtsx_pcr {
#define PCR_REVERSE_SOCKET (1 << 1)
u32 flags;
+ u32 tx_initial_phase;
+ u32 rx_initial_phase;
+
const u32 *sd_pull_ctl_enable_tbl;
const u32 *sd_pull_ctl_disable_tbl;
const u32 *ms_pull_ctl_enable_tbl;
@@ -863,6 +866,18 @@ struct rtsx_pcr {
#define PCI_VID(pcr) ((pcr)->pci->vendor)
#define PCI_PID(pcr) ((pcr)->pci->device)
+#define SDR104_PHASE(val) ((val) & 0xFF)
+#define SDR50_PHASE(val) (((val) >> 8) & 0xFF)
+#define DDR50_PHASE(val) (((val) >> 16) & 0xFF)
+#define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase)
+#define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase)
+#define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase)
+#define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase)
+#define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase)
+#define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase)
+#define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \
+ (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
+
void rtsx_pci_start_run(struct rtsx_pcr *pcr);
int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);