diff options
| author |   Benjamin Gaignard <benjamin.gaignard@linaro.org> | 2017-04-04 09:47:51 +0200 |
|---|---|---|
| committer |   Jonathan Cameron <jic23@kernel.org> | 2017-04-14 15:08:31 +0100 |
| commit | 4adec7da0536a345d901d7ba55b6c93a14eeeaff (patch) | |
| tree | f8eb05106b3e15c05e3241569aceebacf629bedc /include/linux/mfd/stm32-timers.h | |
| parent | iio: imu: st_lsm6dsx: use i2c/spi device name for iio_dev name (diff) | |
| download | linux-dev-4adec7da0536a345d901d7ba55b6c93a14eeeaff.tar.xz linux-dev-4adec7da0536a345d901d7ba55b6c93a14eeeaff.zip | |
iio: stm32 trigger: Add quadrature encoder device
One of the features of STM32 trigger hardware block is a quadrature
encoder that can counts up/down depending of the levels and edges
of the selected external pins.
This patch allow to read/write the counter, get it direction,
set/get quadrature modes and get scale factor.
When counting up preset value is the limit of the counter.
When counting down the counter start from preset value down to 0.
This preset value could be set/get by using
/sys/bus/iio/devices/iio:deviceX/in_count0_preset attribute.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Reviewed-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'include/linux/mfd/stm32-timers.h')
| -rw-r--r-- | include/linux/mfd/stm32-timers.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index d0300045f04a..4a0abbc10ef6 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -21,6 +21,7 @@ #define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ #define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ #define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ +#define TIM_CNT 0x24 /* Counter */ #define TIM_PSC 0x28 /* Prescaler */ #define TIM_ARR 0x2c /* Auto-Reload Register */ #define TIM_CCR1 0x34 /* Capt/Comp Register 1 */ @@ -30,6 +31,7 @@ #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ #define TIM_CR1_CEN BIT(0) /* Counter Enable */ +#define TIM_CR1_DIR BIT(4) /* Counter Direction */ #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ #define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ |