diff options
| author |   Miquel Raynal <miquel.raynal@bootlin.com> | 2021-10-15 10:14:49 +0200 |
|---|---|---|
| committer |   Lee Jones <lee.jones@linaro.org> | 2021-10-21 09:21:13 +0100 |
| commit | 2f89c2619ce93bf2b0e6e721614fc33e8cf48f03 (patch) | |
| tree | 9df287547188c27e41d4b77b865f31de40c9f3ea /include/linux/mfd | |
| parent | mfd: ti_am335x_tscadc: Rename the subsystem enable macro (diff) | |
| download | linux-dev-2f89c2619ce93bf2b0e6e721614fc33e8cf48f03.tar.xz linux-dev-2f89c2619ce93bf2b0e6e721614fc33e8cf48f03.zip | |
mfd: ti_am335x_tscadc: Add TSC prefix in certain macros
While the register list (and names) between ADC0 and ADC1 are pretty
close, the bits inside changed a little bit. To avoid any future
confusion, let's add the TSC prefix when some bits are in a register
that is common to both revisions of the ADC, but are specific to the
am33xx hardware.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20211015081506.933180-32-miquel.raynal@bootlin.com
Diffstat (limited to 'include/linux/mfd')
| -rw-r--r-- | include/linux/mfd/ti_am335x_tscadc.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/linux/mfd/ti_am335x_tscadc.h b/include/linux/mfd/ti_am335x_tscadc.h index 860289ae8516..cc6de9258455 100644 --- a/include/linux/mfd/ti_am335x_tscadc.h +++ b/include/linux/mfd/ti_am335x_tscadc.h @@ -98,13 +98,13 @@ /* Control register */ #define CNTRLREG_SSENB BIT(0) #define CNTRLREG_STEPID BIT(1) -#define CNTRLREG_STEPCONFIGWRT BIT(2) +#define CNTRLREG_TSC_STEPCONFIGWRT BIT(2) #define CNTRLREG_POWERDOWN BIT(4) -#define CNTRLREG_AFE_CTRL(val) FIELD_PREP(GENMASK(6, 5), (val)) -#define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1) -#define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2) -#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3) -#define CNTRLREG_TSCENB BIT(7) +#define CNTRLREG_TSC_AFE_CTRL(val) FIELD_PREP(GENMASK(6, 5), (val)) +#define CNTRLREG_TSC_4WIRE CNTRLREG_TSC_AFE_CTRL(1) +#define CNTRLREG_TSC_5WIRE CNTRLREG_TSC_AFE_CTRL(2) +#define CNTRLREG_TSC_8WIRE CNTRLREG_TSC_AFE_CTRL(3) +#define CNTRLREG_TSC_ENB BIT(7) /* FIFO READ Register */ #define FIFOREAD_DATA_MASK GENMASK(11, 0) @@ -118,7 +118,7 @@ #define SEQ_STATUS BIT(5) #define CHARGE_STEP 0x11 -#define ADC_CLK (3 * HZ_PER_MHZ) +#define TSC_ADC_CLK (3 * HZ_PER_MHZ) #define TOTAL_STEPS 16 #define TOTAL_CHANNELS 8 #define FIFO1_THRESHOLD 19 |