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| author |   Eran Ben Elisha <eranbe@nvidia.com> | 2020-11-20 15:03:28 -0800 |
|---|---|---|
| committer |   Saeed Mahameed <saeedm@nvidia.com> | 2020-11-26 18:43:48 -0800 |
| commit | 59d2ae1db89f5a491d48f798ffccef36cc69ca65 (patch) | |
| tree | 64ff1b4b00861095fbcc65279a0f19b9785d4bc8 /include/linux/mlx5/mlx5_ifc.h | |
| parent | net/mlx5: Add misc4 to mlx5_ifc_fte_match_param_bits (diff) | |
| download | linux-dev-59d2ae1db89f5a491d48f798ffccef36cc69ca65.tar.xz linux-dev-59d2ae1db89f5a491d48f798ffccef36cc69ca65.zip | |
net/mlx5: Add ts_cqe_to_dest_cqn related bits
Add a bit in HCA capabilities layout to indicate if ts_cqe_to_dest_cqn is
supported.
In addition, add ts_cqe_to_dest_cqn field to SQ context, for driver to
set the actual CQN.
Signed-off-by: Eran Ben Elisha <eranbe@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Diffstat (limited to 'include/linux/mlx5/mlx5_ifc.h')
| -rw-r--r-- | include/linux/mlx5/mlx5_ifc.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 11c24fafd7f2..632b9a61fda5 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1261,7 +1261,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 ece_support[0x1]; u8 reserved_at_a4[0x7]; u8 log_max_srq[0x5]; - u8 reserved_at_b0[0x10]; + u8 reserved_at_b0[0x2]; + u8 ts_cqe_to_dest_cqn[0x1]; + u8 reserved_at_b3[0xd]; u8 max_sgl_for_optimized_performance[0x8]; u8 log_max_cq_sz[0x8]; @@ -3312,8 +3314,12 @@ struct mlx5_ifc_sqc_bits { u8 reserved_at_80[0x10]; u8 hairpin_peer_vhca[0x10]; - u8 reserved_at_a0[0x50]; + u8 reserved_at_a0[0x20]; + u8 reserved_at_c0[0x8]; + u8 ts_cqe_to_dest_cqn[0x18]; + + u8 reserved_at_e0[0x10]; u8 packet_pacing_rate_limit_index[0x10]; u8 tis_lst_sz[0x10]; u8 reserved_at_110[0x10]; |