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| author |   Aharon Landau <aharonl@nvidia.com> | 2021-06-16 10:57:38 +0300 |
|---|---|---|
| committer |   Leon Romanovsky <leonro@nvidia.com> | 2021-06-22 09:35:16 +0300 |
| commit | 9a1ac95a59d0724ffac2181a98b232c3f94f49f5 (patch) | |
| tree | 58b30e71cd768e5d856a0948df210c085e613eb1 /include/linux/mlx5/mlx5_ifc.h | |
| parent | Linux 5.13-rc6 (diff) | |
| download | linux-dev-9a1ac95a59d0724ffac2181a98b232c3f94f49f5.tar.xz linux-dev-9a1ac95a59d0724ffac2181a98b232c3f94f49f5.zip | |
RDMA/mlx5: Refactor get_ts_format functions to simplify code
QPC, SQC and RQC timestamp formats and capabilities are always equal
because they represent general hardware support. So instead of code
duplication, let's merge them into general enum and logic.
Signed-off-by: Aharon Landau <aharonl@nvidia.com>
Reviewed-by: Maor Gottlieb <maorg@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Diffstat (limited to 'include/linux/mlx5/mlx5_ifc.h')
| -rw-r--r-- | include/linux/mlx5/mlx5_ifc.h | 36 |
1 files changed, 6 insertions, 30 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index eb86e80e4643..668e1d016066 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -953,9 +953,9 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits { }; enum { - MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, - MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, - MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, + MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, + MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, + MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, }; struct mlx5_ifc_roce_cap_bits { @@ -1296,18 +1296,6 @@ enum { MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, }; -enum { - MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, - MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, - MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, -}; - -enum { - MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, - MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, - MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, -}; - struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_0[0x1f]; u8 vhca_resource_manager[0x1]; @@ -2944,9 +2932,9 @@ enum { }; enum { - MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, - MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, - MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, + MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, + MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, + MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, }; struct mlx5_ifc_qpc_bits { @@ -3396,12 +3384,6 @@ enum { MLX5_SQC_STATE_ERR = 0x3, }; -enum { - MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, - MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, - MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, -}; - struct mlx5_ifc_sqc_bits { u8 rlky[0x1]; u8 cd_master[0x1]; @@ -3507,12 +3489,6 @@ enum { MLX5_RQC_STATE_ERR = 0x3, }; -enum { - MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, - MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, - MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, -}; - struct mlx5_ifc_rqc_bits { u8 rlky[0x1]; u8 delay_drop_en[0x1]; |