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| author |   Miquel Raynal <miquel.raynal@bootlin.com> | 2021-05-05 23:37:41 +0200 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2021-05-26 10:43:54 +0200 |
| commit | d7a773e8812bcf7a5412e4baebc6eb1c11242551 (patch) | |
| tree | 02cd55f67063aabbebe49a0b04655f33249c8f89 /include/linux/mtd | |
| parent | mtd: rawnand: Avoid accessing NV-DDR timings from legacy code (diff) | |
| download | linux-dev-d7a773e8812bcf7a5412e4baebc6eb1c11242551.tar.xz linux-dev-d7a773e8812bcf7a5412e4baebc6eb1c11242551.zip | |
mtd: rawnand: Access SDR and NV-DDR timings through a common macro
Most timings related to the bus timings are different between SDR and
NV-DDR. However, we identified 9 individual timings which are more
related to the NAND chip internals. These are common between the two
interface types. Fortunately, only these common timings are being shared
through the NAND core and its ->exec_op() interface, which allows the
writing of a simple macro checking the interface type and depending on
it, returning either the relevant SDR timing or the NV-DDR timing. This
is the purpose of the NAND_COMMON_TIMING_PS() macro.
As all this is evaluated at build time, one will immediately be notified
in case a non common timing is being accessed through this macro.
Two handy macros are also inserted at the same time, which use
PSEC_TO_NSEC or PSEC_TO_MSEC so that it is very easy to return timings
in milli-, nano- or pico-seconds, as usually requested by the internal
API.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-14-miquel.raynal@bootlin.com
Diffstat (limited to 'include/linux/mtd')
| -rw-r--r-- | include/linux/mtd/rawnand.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index a53a1543d1d4..89b9c52c7387 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -557,6 +557,34 @@ struct nand_nvddr_timings { u32 tWW_min; }; +/* + * While timings related to the data interface itself are mostly different + * between SDR and NV-DDR, timings related to the internal chip behavior are + * common. IOW, the following entries which describe the internal delays have + * the same definition and are shared in both SDR and NV-DDR timing structures: + * - tADL_min + * - tBERS_max + * - tCCS_min + * - tFEAT_max + * - tPROG_max + * - tR_max + * - tRR_min + * - tRST_max + * - tWB_max + * + * The below macros return the value of a given timing, no matter the interface. + */ +#define NAND_COMMON_TIMING_PS(conf, timing_name) \ + nand_interface_is_sdr(conf) ? \ + nand_get_sdr_timings(conf)->timing_name : \ + nand_get_nvddr_timings(conf)->timing_name + +#define NAND_COMMON_TIMING_MS(conf, timing_name) \ + PSEC_TO_MSEC(NAND_COMMON_TIMING_PS((conf), timing_name)) + +#define NAND_COMMON_TIMING_NS(conf, timing_name) \ + PSEC_TO_NSEC(NAND_COMMON_TIMING_PS((conf), timing_name)) + /** * enum nand_interface_type - NAND interface type * @NAND_SDR_IFACE: Single Data Rate interface |