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| author |   Jay Cornwall <Jay.Cornwall@amd.com> | 2018-01-04 19:44:59 -0500 |
|---|---|---|
| committer |   Bjorn Helgaas <bhelgaas@google.com> | 2018-01-23 14:46:50 -0600 |
| commit | 430a23689dea2e36ae5a0fc75a67301fd46b18bf (patch) | |
| tree | 9e69138e3790ea06d9f1d6711364c35e0cb41ee1 /include/linux/pci.h | |
| parent | PCI: Make PCI_SCAN_ALL_PCIE_DEVS work for Root as well as Downstream Ports (diff) | |
| download | linux-dev-430a23689dea2e36ae5a0fc75a67301fd46b18bf.tar.xz linux-dev-430a23689dea2e36ae5a0fc75a67301fd46b18bf.zip | |
PCI: Add pci_enable_atomic_ops_to_root()
The Atomic Operations feature (PCIe r4.0, sec 6.15) allows atomic
transctions to be requested by, routed through and completed by PCIe
components. Routing and completion do not require software support.
Component support for each is detectable via the DEVCAP2 register.
A Requester may use AtomicOps only if its PCI_EXP_DEVCTL2_ATOMIC_REQ is
set. This should be set only if the Completer and all intermediate routing
elements support AtomicOps.
A concrete example is the AMD Fiji-class GPU (which is capable of making
AtomicOp requests), below a PLX 8747 switch (advertising AtomicOp routing)
with a Haswell host bridge (advertising AtomicOp completion support).
Add pci_enable_atomic_ops_to_root() for per-device control over AtomicOp
requests. This checks to be sure the Root Port supports completion of the
desired AtomicOp sizes and the path to the Root Port supports routing the
AtomicOps.
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
[bhelgaas: changelog, comments, whitespace]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/linux/pci.h')
| -rw-r--r-- | include/linux/pci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h index c170c9250c8b..ab3d12a7dfed 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2061,6 +2061,7 @@ void pci_request_acs(void); bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); bool pci_acs_path_enabled(struct pci_dev *start, struct pci_dev *end, u16 acs_flags); +int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask); #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) |