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| author |   Rafael J. Wysocki <rjw@sisk.pl> | 2010-12-19 15:57:16 +0100 |
|---|---|---|
| committer |   Jesse Barnes <jbarnes@virtuousgeek.org> | 2010-12-23 12:54:03 -0800 |
| commit | fe31e69740eddc7316071ed5165fed6703c8cd12 (patch) | |
| tree | b58f193d7176bfe19ae975fec7ff42d7e242e359 /include/linux/pci_regs.h | |
| parent | PCI: pci-stub: ignore zero-length id parameters (diff) | |
| download | linux-dev-fe31e69740eddc7316071ed5165fed6703c8cd12.tar.xz linux-dev-fe31e69740eddc7316071ed5165fed6703c8cd12.zip | |
PCI/PCIe: Clear Root PME Status bits early during system resume
I noticed that PCI Express PMEs don't work on my Toshiba Portege R500
after the system has been woken up from a sleep state by a PME
(through Wake-on-LAN). After some investigation it turned out that
the BIOS didn't clear the Root PME Status bit in the root port that
received the wakeup PME and since the Requester ID was also set in
the port's Root Status register, any subsequent PMEs didn't trigger
interrupts.
This problem can be avoided by clearing the Root PME Status bits in
all PCI Express root ports during early resume. For this purpose,
add an early resume routine to the PCIe port driver and make this
driver be always registered, even if pci_ports_disable is set (in
which case the driver's only function is to provide the early
resume callback).
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'include/linux/pci_regs.h')
| -rw-r--r-- | include/linux/pci_regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index d4f2c80a6c3e..5b7e6b1ba54f 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -504,6 +504,8 @@ #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */ #define PCI_EXP_RTCAP 30 /* Root Capabilities */ #define PCI_EXP_RTSTA 32 /* Root Status */ +#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */ +#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */ #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ #define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ |