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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-30 12:41:51 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-05-05 12:10:21 +0200 |
| commit | 60191843db7812dba4fdd2790a2d646721e13b21 (patch) | |
| tree | ea1d30c809736129631a94f7b2a07c3ea802e8ae /include/linux/phy/git:/ssh:/git@git.zx2c4.com | |
| parent | clk: renesas: rzg2l: Add DSI divider clk support (diff) | |
| download | linux-dev-60191843db7812dba4fdd2790a2d646721e13b21.tar.xz linux-dev-60191843db7812dba4fdd2790a2d646721e13b21.zip | |
clk: renesas: r9a07g044: Add M1 clock support
Add support for M1 clock which is sourced from FOUTPOSTDIV.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'include/linux/phy/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions