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| author | 2022-02-22 10:26:24 +0530 | |
|---|---|---|
| committer | 2022-04-12 21:22:34 -0500 | |
| commit | ce91bc005e076acd3415d557d7e7c488aa9ab10d (patch) | |
| tree | d4570585c3f044182e0e9792f7f91bd926d503bf /include/linux/phy | |
| parent | ARM: dts: qcom: sdx65: Add support for A7 PLL clock (diff) | |
ARM: dts: qcom: sdx65: Add support for APCS block
The APCS block on SDX65 acts as a mailbox controller and also provides
clock output for the Cortex A7 CPU.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-5-git-send-email-quic_rohiagar@quicinc.com
Diffstat (limited to 'include/linux/phy')
0 files changed, 0 insertions, 0 deletions
