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| author |   Prashant Malani <pmalani@chromium.org> | 2021-04-20 10:16:11 -0700 |
|---|---|---|
| committer |   Enric Balletbo i Serra <enric.balletbo@collabora.com> | 2021-04-20 19:35:42 +0200 |
| commit | 67880f1bc342ed4c94e72cad7f8ca76e5121aae3 (patch) | |
| tree | e7197045430c0a8ce786c5c0e0528f25b7c65525 /include/linux/platform_data/cros_ec_commands.h | |
| parent | platform/chrome: cros_ec_typec: Track port role (diff) | |
| download | linux-dev-67880f1bc342ed4c94e72cad7f8ca76e5121aae3.tar.xz linux-dev-67880f1bc342ed4c94e72cad7f8ca76e5121aae3.zip | |
platform/chrome: cros_ec: Add Type C hard reset
Update the EC command header to include the new event bit. This bit
is included in the latest version of the Chrome EC headers[1].
[1] https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads/main/include/ec_commands.h
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210420171617.3830902-1-pmalani@chromium.org
Diffstat (limited to 'include/linux/platform_data/cros_ec_commands.h')
| -rw-r--r-- | include/linux/platform_data/cros_ec_commands.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h index 5ff8597ceabd..9156078c6fc6 100644 --- a/include/linux/platform_data/cros_ec_commands.h +++ b/include/linux/platform_data/cros_ec_commands.h @@ -5678,6 +5678,7 @@ enum tcpc_cc_polarity { #define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0) #define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1) +#define PD_STATUS_EVENT_HARD_RESET BIT(2) struct ec_params_typec_status { uint8_t port; |