diff options
| author |   Thomas Gleixner <tglx@linutronix.de> | 2013-09-17 18:53:05 +0000 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2013-11-13 20:21:46 +0100 |
| commit | 54197e43a4a9a0f3fc406d72d9815754e84fab1e (patch) | |
| tree | 70db3c0a63b066ac7a8c9e7fabbb8127d73717da /include/linux/preempt_mask.h | |
| parent | m68k: Simplify low level interrupt handling code (diff) | |
| download | linux-dev-54197e43a4a9a0f3fc406d72d9815754e84fab1e.tar.xz linux-dev-54197e43a4a9a0f3fc406d72d9815754e84fab1e.zip | |
hardirq: Make hardirq bits generic
There is no reason for per arch hardirq bits. Make them all generic
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20130917183628.534494408@linutronix.de
Diffstat (limited to 'include/linux/preempt_mask.h')
| -rw-r--r-- | include/linux/preempt_mask.h | 30 |
1 files changed, 8 insertions, 22 deletions
diff --git a/include/linux/preempt_mask.h b/include/linux/preempt_mask.h index 931bc616219f..810d7e386f20 100644 --- a/include/linux/preempt_mask.h +++ b/include/linux/preempt_mask.h @@ -11,36 +11,22 @@ * - bits 0-7 are the preemption count (max preemption depth: 256) * - bits 8-15 are the softirq count (max # of softirqs: 256) * - * The hardirq count can in theory reach the same as NR_IRQS. - * In reality, the number of nested IRQS is limited to the stack - * size as well. For archs with over 1000 IRQS it is not practical - * to expect that they will all nest. We give a max of 10 bits for - * hardirq nesting. An arch may choose to give less than 10 bits. - * m68k expects it to be 8. - * - * - bits 16-25 are the hardirq count (max # of nested hardirqs: 1024) - * - bit 26 is the NMI_MASK - * - bit 27 is the PREEMPT_ACTIVE flag + * The hardirq count could in theory be the same as the number of + * interrupts in the system, but we run all interrupt handlers with + * interrupts disabled, so we cannot have nesting interrupts. Though + * there are a few palaeontologic drivers which reenable interrupts in + * the handler, so we need more than one bit here. * * PREEMPT_MASK: 0x000000ff * SOFTIRQ_MASK: 0x0000ff00 - * HARDIRQ_MASK: 0x03ff0000 - * NMI_MASK: 0x04000000 + * HARDIRQ_MASK: 0x000f0000 + * NMI_MASK: 0x00100000 */ #define PREEMPT_BITS 8 #define SOFTIRQ_BITS 8 +#define HARDIRQ_BITS 4 #define NMI_BITS 1 -#define MAX_HARDIRQ_BITS 10 - -#ifndef HARDIRQ_BITS -# define HARDIRQ_BITS MAX_HARDIRQ_BITS -#endif - -#if HARDIRQ_BITS > MAX_HARDIRQ_BITS -#error HARDIRQ_BITS too high! -#endif - #define PREEMPT_SHIFT 0 #define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS) #define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS) |