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| author |   Andre Przywara <andre.przywara@arm.com> | 2021-01-06 14:32:46 +0000 |
|---|---|---|
| committer |   Maxime Ripard <maxime@cerno.tech> | 2021-01-06 17:51:23 +0100 |
| commit | 756650820abd4770c4200763505b634a3c04e05e (patch) | |
| tree | 7b59b3a8c0fb7de9b179cefb7a88c4a53e6f3df7 /include/linux/raid/git:/git.zx2c4.com/ssh:/git@git.zx2c4.com | |
| parent | clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset (diff) | |
| download | linux-dev-756650820abd4770c4200763505b634a3c04e05e.tar.xz linux-dev-756650820abd4770c4200763505b634a3c04e05e.zip | |
clk: sunxi-ng: h6: Fix CEC clock
The CEC clock on the H6 SoC is a bit special, since it uses a fixed
pre-dividier for one source clock (the PLL), but conveys the other clock
(32K OSC) directly.
We are using a fixed predivider array for that, but fail to use the right
flag to actually activate that.
Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Reported-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210106143246.11255-1-andre.przywara@arm.com
Diffstat (limited to 'include/linux/raid/git:/git.zx2c4.com/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions