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| author |   Dan Williams <dan.j.williams@intel.com> | 2022-01-23 16:31:56 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:33 -0800 |
| commit | a4a0ce242fcd7022349212c4e2f795762e6ff050 (patch) | |
| tree | 55cf66625ce867dc0ec684ca8f8bc96af20509b7 /include/linux/raid/git:/git.zx2c4.com/ssh:/git@git.zx2c4.com | |
| parent | tools/testing/cxl: Mock dvsec_ranges() (diff) | |
| download | linux-dev-a4a0ce242fcd7022349212c4e2f795762e6ff050.tar.xz linux-dev-a4a0ce242fcd7022349212c4e2f795762e6ff050.zip | |
tools/testing/cxl: Fix root port to host bridge assignment
Mocked root-ports are meant to be round-robin assigned to host-bridges.
Fixes: 67dcdd4d3b83 ("tools/testing/cxl: Introduce a mocked-up CXL port hierarchy")
Link: https://lore.kernel.org/r/164298431629.3018233.14004377108116384485.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include/linux/raid/git:/git.zx2c4.com/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions