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| author | 2020-09-03 10:38:57 +0300 | |
|---|---|---|
| committer | 2020-09-18 09:40:41 -0300 | |
| commit | 54a38b6627d3f11028f806f1f529a68453a77f46 (patch) | |
| tree | a12de1ea86394d49e50071a08f8ba4137563fa63 /include/linux/timerqueue.h | |
| parent | RDMA/mlx5: Allow DM allocation for sw_owner_v2 enabled devices (diff) | |
RDMA/mlx5: Expose TIR and QP ICM address for sw_owner_v2 devices
Expose the ICM address to access TIR and QP, this will allow sw_owned_v2
devices to steer traffic to TIRs and QPs same as done with sw_owner
capability.
Link: https://lore.kernel.org/r/20200903073857.1129166-4-leon@kernel.org
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions
