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| author |   Bin Meng <bmeng.cn@gmail.com> | 2017-09-11 02:41:55 -0700 |
|---|---|---|
| committer |   Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> | 2017-10-11 09:44:39 +0200 |
| commit | fc2b34726101016b2736d5025dde5a112e313577 (patch) | |
| tree | a830704444f00d317ea0500a42d0390bc8ffd02a /include/linux/timerqueue.h | |
| parent | spi-nor: intel-spi: Check transfer length in the HW/SW cycle (diff) | |
spi-nor: intel-spi: Use SW sequencer for BYT/LPT
Baytrail/Lynx Point SPI controller's HW sequencer only supports basic
operations. This is determined by the chipset design, however current
codes try to use register values in OPMENU0/OPMENU1 to see whether SW
sequencer should be used, which is wrong. In fact OPMENU0/OPMENU1 can
remain unprogrammed by some bootloaders.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Diffstat (limited to 'include/linux/timerqueue.h')
0 files changed, 0 insertions, 0 deletions