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authorTuomas Tynkkynen <ttynkkynen@nvidia.com>2013-08-12 16:06:51 +0300
committerFelipe Balbi <balbi@ti.com>2013-08-12 13:29:48 -0500
commit3e635202ce40e4d7ff3fafc18db70c5d28cc6622 (patch)
tree9feaee838221202b9a87e5ae49e6f94f212f17b7 /include/linux/usb/tegra_usb_phy.h
parentusb: phy: tegra: Fix wrong PHY parameters (diff)
downloadlinux-dev-3e635202ce40e4d7ff3fafc18db70c5d28cc6622.tar.xz
linux-dev-3e635202ce40e4d7ff3fafc18db70c5d28cc6622.zip
usb: phy: tegra: Tegra30 support
The Tegra30 USB PHY is a bit different than the Tegra20 PHY: - The EHCI controller supports the HOSTPC register extension, and some of the fields that the PHY needs to modify (PHCD and PTS) have moved to the new HOSTPC register. - Some of the UTMI PLL configuration registers have moved from the USB register space to the Clock-And-Reset controller space. In Tegra30 the clock driver is responsible for configuring the UTMI PLL. - The USBMODE register must be explicitly written to enter host mode. - Certain PHY parameters need to be programmed for optimal signal quality. Support for this will be added in the next patch. The new tegra_phy_soc_config structure is added to describe the differences between the SoCs. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'include/linux/usb/tegra_usb_phy.h')
-rw-r--r--include/linux/usb/tegra_usb_phy.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_usb_phy.h
index d3db274610a1..d3a63c354db9 100644
--- a/include/linux/usb/tegra_usb_phy.h
+++ b/include/linux/usb/tegra_usb_phy.h
@@ -18,6 +18,24 @@
#include <linux/clk.h>
#include <linux/usb/otg.h>
+/*
+ * utmi_pll_config_in_car_module: true if the UTMI PLL configuration registers
+ * should be set up by clk-tegra, false if by the PHY code
+ * has_hostpc: true if the USB controller has the HOSTPC extension, which
+ * changes the location of the PHCD and PTS fields
+ * requires_usbmode_setup: true if the USBMODE register needs to be set to
+ * enter host mode
+ * requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level
+ * and hsdiscon_level should be set for adequate signal quality
+ */
+
+struct tegra_phy_soc_config {
+ bool utmi_pll_config_in_car_module;
+ bool has_hostpc;
+ bool requires_usbmode_setup;
+ bool requires_extra_tuning_parameters;
+};
+
struct tegra_utmip_config {
u8 hssync_start_delay;
u8 elastic_limit;
@@ -47,6 +65,7 @@ struct tegra_usb_phy {
struct regulator *vbus;
enum usb_dr_mode mode;
void *config;
+ const struct tegra_phy_soc_config *soc_config;
struct usb_phy *ulpi;
struct usb_phy u_phy;
bool is_legacy_phy;