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authorDaniel Jurgens <danielj@mellanox.com>2016-10-25 18:36:24 +0300
committerDavid S. Miller <davem@davemloft.net>2016-10-29 12:00:39 -0400
commitb47bd6ea40636362a8b6605de51207cc387ba0b8 (patch)
tree6bed00d13dfefc41b5ad060358426d299f1fc0d8 /include/linux
parentsctp: validate chunk len before actually using it (diff)
downloadlinux-dev-b47bd6ea40636362a8b6605de51207cc387ba0b8.tar.xz
linux-dev-b47bd6ea40636362a8b6605de51207cc387ba0b8.zip
{net, ib}/mlx5: Make cache line size determination at runtime.
ARM 64B cache line systems have L1_CACHE_BYTES set to 128. cache_line_size() will return the correct size. Fixes: cf50b5efa2fe('net/mlx5_core/ib: New device capabilities handling.') Signed-off-by: Daniel Jurgens <danielj@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mlx5/driver.h11
1 files changed, 0 insertions, 11 deletions
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 85c4786427e4..5dbda60a09f4 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -626,10 +626,6 @@ struct mlx5_db {
};
enum {
- MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
-};
-
-enum {
MLX5_COMP_EQ_SIZE = 1024,
};
@@ -638,13 +634,6 @@ enum {
MLX5_PTYS_EN = 1 << 2,
};
-struct mlx5_db_pgdir {
- struct list_head list;
- DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
- __be32 *db_page;
- dma_addr_t db_dma;
-};
-
typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
struct mlx5_cmd_work_ent {