diff options
| author |   Thinh Nguyen <Thinh.Nguyen@synopsys.com> | 2018-03-16 15:33:48 -0700 |
|---|---|---|
| committer |   Felipe Balbi <felipe.balbi@linux.intel.com> | 2018-03-22 10:48:46 +0200 |
| commit | fab3833338779e1e668bd58d1f76d601657304b8 (patch) | |
| tree | a7071ba2b0f8b27bfadc3600040378fdf2b5bd65 /include/linux | |
| parent | usb: dwc3: pci: Properly cleanup resource (diff) | |
usb: dwc3: Add SoftReset PHY synchonization delay
From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Diffstat (limited to 'include/linux')
0 files changed, 0 insertions, 0 deletions