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| author |   Alexandre Courbot <acourbot@nvidia.com> | 2015-02-26 12:44:51 +0900 |
|---|---|---|
| committer |   Ben Skeggs <bskeggs@redhat.com> | 2015-04-14 17:00:46 +1000 |
| commit | 996f545fbb0dc9ed4a640b5ef098f51fe28cca5c (patch) | |
| tree | 4ef34ade7df6490c03202d0021b7a96581f9724d /include/uapi/drm/nouveau_drm.h | |
| parent | drm/nouveau/instmem/gk20a: add IOMMU support (diff) | |
| download | linux-dev-996f545fbb0dc9ed4a640b5ef098f51fe28cca5c.tar.xz linux-dev-996f545fbb0dc9ed4a640b5ef098f51fe28cca5c.zip | |
drm/nouveau/gem: allow user-space to specify an object should be coherent
User-space use mappable BOs notably for fences, and expects that a
value update by the GPU will be immediatly visible through the
user-space mapping.
ARM has a property that may prevent this from happening though: memory
can be mapped multiple times only if the different mappings share the
same caching properties. However all the lowmem memory is already
identity-mapped into the kernel with cache enabled, so when user-space
requests an uncached mapping, we actually get an "undefined caching
policy" one and this has strange side-effects described on Freedesktop
bug 86690.
To prevent this from happening, allow user-space to explicitly specify
which objects should be coherent, and create such objects with the
TTM_PL_FLAG_UNCACHED flag. This will make TTM allocate memory using the
DMA API, which will fix the identify mapping and allow us to safely map
the objects to user-space uncached.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'include/uapi/drm/nouveau_drm.h')
| -rw-r--r-- | include/uapi/drm/nouveau_drm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/uapi/drm/nouveau_drm.h b/include/uapi/drm/nouveau_drm.h index 0d7608dc1a34..5507eead5863 100644 --- a/include/uapi/drm/nouveau_drm.h +++ b/include/uapi/drm/nouveau_drm.h @@ -39,6 +39,7 @@ #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) +#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4) #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */ #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 |