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authorAlex Deucher <alexander.deucher@amd.com>2017-03-03 16:00:11 -0500
committerAlex Deucher <alexander.deucher@amd.com>2017-03-29 23:54:39 -0400
commit00ac6f6be1c875495320c257a70c82768fffedb3 (patch)
tree99a78b93f84c93f1f151d51dde08412ec73b5341 /include/uapi/drm
parentdrm/amdgpu: Add asic family for vega10 (diff)
downloadlinux-dev-00ac6f6be1c875495320c257a70c82768fffedb3.tar.xz
linux-dev-00ac6f6be1c875495320c257a70c82768fffedb3.zip
drm/amdgpu: add tiling flags for GFX9 (v2)
v2: Marek: allow shifts >32 in AMDGPU_TILING_SET/GET Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/uapi/drm')
-rw-r--r--include/uapi/drm/amdgpu_drm.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 08e90d8ea52a..770dc56df3dd 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -209,6 +209,7 @@ struct drm_amdgpu_gem_userptr {
__u32 handle;
};
+/* SI-CI-VI: */
/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
@@ -227,10 +228,15 @@ struct drm_amdgpu_gem_userptr {
#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
+/* GFX9 and later: */
+#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
+#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
+
+/* Set/Get helpers for tiling flags. */
#define AMDGPU_TILING_SET(field, value) \
- (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
+ (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
#define AMDGPU_TILING_GET(value, field) \
- (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
+ (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2