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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-25 10:52:44 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-28 16:37:45 +0200 |
| commit | 5d33481f54758eb050473af0692a043c084ad581 (patch) | |
| tree | ee67a62497d12e0678c87cb2921975ac597d71f2 /include/uapi/linux/can/git:/ssh: | |
| parent | clk: renesas: r9a07g043: Add OSTM clock and reset entries (diff) | |
| download | linux-dev-5d33481f54758eb050473af0692a043c084ad581.tar.xz linux-dev-5d33481f54758eb050473af0692a043c084ad581.zip | |
clk: renesas: r9a07g043: Add WDT clock and reset entries
Add WDT{0,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'include/uapi/linux/can/git:/ssh:')
0 files changed, 0 insertions, 0 deletions