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| author |   Jan Kiszka <jan.kiszka@siemens.com> | 2017-02-08 17:09:08 +0100 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-02-10 15:13:26 +0100 |
| commit | 7e12357ed64afdc8e60d64b8f8f17d711acf950a (patch) | |
| tree | b6f86447f9c991328754fddbbfca27fe3fb4c15c /include/uapi/linux/serial_reg.h | |
| parent | serial: pci: Remove unused pci_boards entries (diff) | |
| download | linux-dev-7e12357ed64afdc8e60d64b8f8f17d711acf950a.tar.xz linux-dev-7e12357ed64afdc8e60d64b8f8f17d711acf950a.zip | |
serial: exar: Move register defines from uapi header to consumer site
None of these registers is relevant for the userspace API.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/uapi/linux/serial_reg.h')
| -rw-r--r-- | include/uapi/linux/serial_reg.h | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h index 25b93a764a1a..5db76880b4ad 100644 --- a/include/uapi/linux/serial_reg.h +++ b/include/uapi/linux/serial_reg.h @@ -367,24 +367,6 @@ #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ /* - * These are definitions for the Exar XR17V35X and XR17(C|D)15X - */ -#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ -#define UART_EXAR_SLEEP 0x8b /* Sleep mode */ -#define UART_EXAR_DVID 0x8d /* Device identification */ - -#define UART_EXAR_FCTR 0x08 /* Feature Control Register */ -#define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */ -#define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */ -#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ -#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ -#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ -#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ - -#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ -#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ - -/* * These are definitions for the Altera ALTR_16550_F32/F64/F128 * Normalized from 0x100 to 0x40 because of shift by 2 (32 bit regs). */ |