diff options
| author |   Kirill Marinushkin <k.marinushkin@gmail.com> | 2018-04-04 06:19:39 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2018-04-16 17:52:31 +0100 |
| commit | e590522a06adce8ca2eb47e77d80616cd1542d91 (patch) | |
| tree | 2430d1b9ab55e3708fe5d6995dfd3234c8fdb8b0 /include/uapi/sound | |
| parent | ASoC: topology: Add missing clock gating parameter when parsing hw_configs (diff) | |
| download | linux-dev-e590522a06adce8ca2eb47e77d80616cd1542d91.tar.xz linux-dev-e590522a06adce8ca2eb47e77d80616cd1542d91.zip | |
ASoC: topology: Add definitions for mclk_direction values
Current comment makes not clear the direction of mclk. Previously, similar
description caused a misunderstanding for bclk_master and fsync_master.
This commit solves the potential confusion the same way it is solved for
bclk_master and fsync_master.
Signed-off-by: Kirill Marinushkin <k.marinushkin@gmail.com>
Acked-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Mark Brown <broonie@kernel.org>
Cc: Pan Xiuli <xiuli.pan@linux.intel.com>
Cc: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Cc: linux-kernel@vger.kernel.org
Cc: alsa-devel@alsa-project.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/uapi/sound')
| -rw-r--r-- | include/uapi/sound/asoc.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/uapi/sound/asoc.h b/include/uapi/sound/asoc.h index f3c4b46e39d8..b901cdbe532a 100644 --- a/include/uapi/sound/asoc.h +++ b/include/uapi/sound/asoc.h @@ -144,6 +144,10 @@ #define SND_SOC_TPLG_DAI_CLK_GATE_GATED 1 #define SND_SOC_TPLG_DAI_CLK_GATE_CONT 2 +/* DAI mclk_direction */ +#define SND_SOC_TPLG_MCLK_CO 0 /* for codec, mclk is output */ +#define SND_SOC_TPLG_MCLK_CI 1 /* for codec, mclk is input */ + /* DAI physical PCM data formats. * Add new formats to the end of the list. */ @@ -334,7 +338,7 @@ struct snd_soc_tplg_hw_config { __u8 invert_fsync; /* 1 for inverted frame clock, 0 for normal */ __u8 bclk_master; /* SND_SOC_TPLG_BCLK_ value */ __u8 fsync_master; /* SND_SOC_TPLG_FSYNC_ value */ - __u8 mclk_direction; /* 0 for input, 1 for output */ + __u8 mclk_direction; /* SND_SOC_TPLG_MCLK_ value */ __le16 reserved; /* for 32bit alignment */ __le32 mclk_rate; /* MCLK or SYSCLK freqency in Hz */ __le32 bclk_rate; /* BCLK freqency in Hz */ |