path: root/include
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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-11-15 16:08:49 -0800
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-11-15 16:08:49 -0800
commit40787d0099676c9923e31fbdb90422d5c97cdcd5 (patch)
tree029b96d58712e390878795e76b46e8598601daeb /include
parentMerge git://git.kernel.org/pub/scm/linux/kernel/git/mingo/linux-2.6-sched (diff)
parent[MIPS] N32 needs to use the compat version of sys_nfsservctl. (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] N32 needs to use the compat version of sys_nfsservctl. [MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts. [MIPS] Sibyte: Fix name of clocksource. [MIPS] SNI: s/achknowledge/acknowledge/ [MIPS] Makefile: Fix canonical system names [MIPS] vpe: handle halting TCs in an errata safe way. [MIPS] Sibyte: Stop timers before programming next even. [MIPS] Sibyte: Increase minimum oneshot timer interval to two ticks. [MIPS] Lasat: Fix overlap of interrupt number ranges. [MIPS] SNI PCIT CPLUS: workaround for b0rked irq wiring of onboard PCI bus 1 [MIPS] Fix shadow register support. [MIPS] Change get_cycles to always return 0. [MIPS] Fix typo in R3000 TRACE_IRQFLAGS code [MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR. [MIPS] iounmap if in vr41xx_pciu_init() pci clock is over 33MHz [MIPS] BCM1480: Remove duplicate acknowledge of timer interrupt. [MIPS] Sibyte: pin timer interrupt to their cores. [MIPS] Qemu: Add early printk, your friend in a cold night. [MIPS] Convert reference to mem_map to pfn_to_page(). [MIPS] Sibyte: resurrect old cache hack.
Diffstat (limited to 'include')
4 files changed, 15 insertions, 6 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 94f1c8172360..ed5c02c6afbb 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -54,6 +54,7 @@ struct cpuinfo_mips {
struct cache_desc dcache; /* Primary D or combined I/D cache */
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
+ int srsets; /* Shadow register sets */
#if defined(CONFIG_MIPS_MT_SMTC)
* In the MIPS MT "SMTC" model, each TC is considered
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
index 581dc45685a2..e0d2458b43d0 100644
--- a/include/asm-mips/lasat/lasatint.h
+++ b/include/asm-mips/lasat/lasatint.h
@@ -1,11 +1,6 @@
-#include <linux/irq.h>
/* lasat 100 */
#define LASAT_INT_STATUS_REG_100 (KSEG1ADDR(0x1c880000))
#define LASAT_INT_MASK_REG_100 (KSEG1ADDR(0x1c890000))
diff --git a/include/asm-mips/mach-lasat/irq.h b/include/asm-mips/mach-lasat/irq.h
new file mode 100644
index 000000000000..da75f89f3723
--- /dev/null
+++ b/include/asm-mips/mach-lasat/irq.h
@@ -0,0 +1,13 @@
+#define LASAT_IRQ_BASE 8
+#define LASAT_IRQ_END 23
+#define NR_IRQS 24
+#include_next <irq.h>
+#endif /* _ASM_MACH_LASAT_IRQ_H */
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
index 5816ad1569d6..6529704aa73a 100644
--- a/include/asm-mips/timex.h
+++ b/include/asm-mips/timex.h
@@ -35,7 +35,7 @@ typedef unsigned int cycles_t;
static inline cycles_t get_cycles(void)
- return read_c0_count();
+ return 0;
#endif /* __KERNEL__ */