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| author |   David Woodhouse <David.Woodhouse@intel.com> | 2016-02-15 12:42:38 +0000 |
|---|---|---|
| committer | David Woodhouse <David.Woodhouse@intel.com> | 2016-02-15 12:42:38 +0000 |
| commit | 46924008273ed03bd11dbb32136e3da4cfe056e1 (patch) | |
| tree | 9d77cb792ac4ccf28aa687942d1c6f1adaf5dd67 /include | |
| parent | iommu/vt-d: Fix 64-bit accesses to 32-bit DMAR_GSTS_REG (diff) | |
| download | linux-dev-46924008273ed03bd11dbb32136e3da4cfe056e1.tar.xz linux-dev-46924008273ed03bd11dbb32136e3da4cfe056e1.zip | |
iommu/vt-d: Clear PPR bit to ensure we get more page request interrupts
According to the VT-d specification we need to clear the PPR bit in
the Page Request Status register when handling page requests, or the
hardware won't generate any more interrupts.
This wasn't actually necessary on SKL/KBL (which may well be the
subject of a hardware erratum, although it's harmless enough). But
other implementations do appear to get it right, and we only ever get
one interrupt unless we clear the PPR bit.
Reported-by: CQ Tang <cq.tang@intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/intel-iommu.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 821273ca4873..2d9b650047a5 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -235,6 +235,9 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) /* low 64 bit */ #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT)) +/* PRS_REG */ +#define DMA_PRS_PPR ((u32)1) + #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ do { \ cycles_t start_time = get_cycles(); \ |