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authorKumar Gala <galak@kernel.crashing.org>2007-06-26 12:12:55 -0500
committerKumar Gala <galak@kernel.crashing.org>2007-06-29 01:58:24 -0500
commit476f5779b77a919f0ced5953de2bf3e0f2d02c07 (patch)
tree10135692a58501576e4fc0f999a60e85e9fde643 /include
parent[POWERPC] 86xx: Avoid system halt if link training isn't at least L0. (diff)
downloadlinux-dev-476f5779b77a919f0ced5953de2bf3e0f2d02c07.tar.xz
linux-dev-476f5779b77a919f0ced5953de2bf3e0f2d02c07.zip
[POWERPC] 86xx: Workaround PCI_PRIMARY_BUS usage
The Freescale PCI-e controllers have an issue in that they use the PCI_PRIMARY_BUS register in the virtual P2P bridge to determine which bus number to match on when generating a type 0 config cycle. The issue is if we are renumbering bus numbers to match Linux we will try setting the PCI_PRIMARY_BUS and will not know which bus number to use for generating type 0 config cycles. We surpress writing the register in the P2P bridge and always keep it at zero. In the future when proper PCI domain support is working we should be able to remove this. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc/pci-bridge.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h
index 0dee56b839a4..c09fbf02ef24 100644
--- a/include/asm-ppc/pci-bridge.h
+++ b/include/asm-ppc/pci-bridge.h
@@ -73,9 +73,14 @@ struct pci_controller {
* Used for variants of PCI indirect handling and possible quirks:
* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
* EXT_REG - provides access to PCI-e extended registers
+ * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
+ * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
+ * to determine which bus number to match on when generating type0
+ * config cycles
*/
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
+#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
u32 indirect_type;
/* Currently, we limit ourselves to 1 IO range and 3 mem