diff options
| author |   Stephen Boyd <sboyd@codeaurora.org> | 2015-08-25 15:55:28 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-08-25 15:55:28 -0700 |
| commit | a7c602bf42f943e717eed92165ebfa6dbaba3029 (patch) | |
| tree | 3c32bc1572acb102ba86c53005ca83cf0c632fd1 /include | |
| parent | clk: qcom: Fix MSM8916 prng clock enable bit (diff) | |
| parent | clk: tegra: Add the DFLL as a possible parent of the cclk_g clock (diff) | |
Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.3-rc1
This contains the DFLL driver needed to implement CPU frequency scaling
on Tegra.
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/reset/tegra124-car.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h new file mode 100644 index 000000000000..070e4f6e7486 --- /dev/null +++ b/include/dt-bindings/reset/tegra124-car.h @@ -0,0 +1,12 @@ +/* + * This header provides Tegra124-specific constants for binding + * nvidia,tegra124-car. + */ + +#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H +#define _DT_BINDINGS_RESET_TEGRA124_CAR_H + +#define TEGRA124_RESET(x) (6 * 32 + (x)) +#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0) + +#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */ |