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| author |   David S. Miller <davem@davemloft.net> | 2016-11-24 15:46:03 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-11-24 15:46:03 -0500 |
| commit | ac32378f3eca55123fe917a6bb38e581118de9e3 (patch) | |
| tree | ae4e8ac4f37f20e46ef4a2849cf2ebfdcc718e71 /include | |
| parent | tcp: enhance tcp_collapse_retrans() with skb_shift() (diff) | |
| parent | net: dsa: bcm_sf2: Ensure we re-negotiate EEE during after link change (diff) | |
| download | linux-dev-ac32378f3eca55123fe917a6bb38e581118de9e3.tar.xz linux-dev-ac32378f3eca55123fe917a6bb38e581118de9e3.zip | |
Merge branch 'phy-broadcom-wirespeed-downshift-support'
Florian Fainelli says:
====================
net: phy: broadcom: Wirespeed/downshift support
This patch series adds support for the Broadcom Wirespeed, aka
downsfhit feature utilizing the recently added ethtool PHY tunables.
Tested with two Gigabit link partners with a 4-wire cable having only
2 pairs connected.
Last patch in the series is a fix that was required for testing, which
should make it to -stable, which I can submit separate against net if
you prefer David.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/brcmphy.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h index 848dc508ef57..f9f8aaf9c943 100644 --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h @@ -114,6 +114,7 @@ #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007 #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8) +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN (1 << 4) #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007 @@ -130,6 +131,7 @@ #define BCM_LED_SRC_INTR 0x6 #define BCM_LED_SRC_QUALITY 0x7 #define BCM_LED_SRC_RCVLED 0x8 +#define BCM_LED_SRC_WIRESPEED 0x9 #define BCM_LED_SRC_MULTICOLOR1 0xa #define BCM_LED_SRC_OPENSHORT 0xb #define BCM_LED_SRC_OFF 0xe /* Tied high */ @@ -141,6 +143,14 @@ * Shadow values go into bits [14:10] of register 0x1c to select a shadow * register to access. */ + +/* 00100: Reserved control register 2 */ +#define BCM54XX_SHD_SCR2 0x04 +#define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100 +#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2 +#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2 +#define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7 + /* 00101: Spare Control Register 3 */ #define BCM54XX_SHD_SCR3 0x05 #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001 |