path: root/include
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authorRalf Baechle <ralf@linux-mips.org>2007-11-08 18:02:29 +0000
committerRalf Baechle <ralf@linux-mips.org>2007-11-15 23:21:49 +0000
commitf6771dbb27c704ce837ba3bb1dcaa53f48f76ea8 (patch)
treeefec5eacc34a9e412a193a79d575cbf3b90acf23 /include
parent[MIPS] Change get_cycles to always return 0. (diff)
[MIPS] Fix shadow register support.
Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 94f1c8172360..ed5c02c6afbb 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -54,6 +54,7 @@ struct cpuinfo_mips {
struct cache_desc dcache; /* Primary D or combined I/D cache */
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
+ int srsets; /* Shadow register sets */
#if defined(CONFIG_MIPS_MT_SMTC)
* In the MIPS MT "SMTC" model, each TC is considered