diff options
| author |   Russell King <rmk+kernel@arm.linux.org.uk> | 2014-03-19 15:39:09 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2014-05-30 00:48:50 +0100 |
| commit | 4374d64933b1d0f0ebbad064289ef44b869d77c1 (patch) | |
| tree | 51f5cdcfc6ce98abd5a7cd4214eeff51af9b1ea2 /kernel/sysctl_binary.c | |
| parent | ARM: l2c: move L2 cache register saving to a more sensible location (diff) | |
ARM: l2c: add automatic enable of early BRESP
The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted. Early
BRESP allows the L2C-310 to send the write response as soon as the
store buffer accepts the write address.
Cortex-A9 processors can signal to the L2C-310 that they wish to be
notified early, and if this optimisation is enabled, the L2C-310 can
signal an early write response.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'kernel/sysctl_binary.c')
0 files changed, 0 insertions, 0 deletions