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author | 2011-02-22 11:29:42 +0000 | |
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committer | 2011-02-23 14:29:50 -0800 | |
commit | 108f518cc4f81eb8e3b46a0bd5cb902ef90a51a8 (patch) | |
tree | e7b48499a74f577c006b4828ee3d140f93eab725 /kernel | |
parent | DM9000B: Fix reg_save after spin_lock in dm9000_timeout (diff) | |
download | linux-dev-108f518cc4f81eb8e3b46a0bd5cb902ef90a51a8.tar.xz linux-dev-108f518cc4f81eb8e3b46a0bd5cb902ef90a51a8.zip |
DM9000B: Fix PHY power for network down/up
DM9000 revision B needs 1 ms delay after PHY power-on.
PHY must be powered on by writing 0 into register DM9000_GPR before
all other settings will change (see Davicom spec and example code).
Remember, that register DM9000_GPR was not changed by reset sequence.
Without this fix the FIFO is out of sync and sends wrong data after
sequence of "ifconfig ethX down ; ifconfig ethX up".
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'kernel')
0 files changed, 0 insertions, 0 deletions