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| author |   Peter Zijlstra <peterz@infradead.org> | 2022-03-08 16:30:35 +0100 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-03-15 10:32:39 +0100 |
| commit | 991625f3dd2cbc4b787deb0213e2bcf8fa264b21 (patch) | |
| tree | f328f63188d911d258d895b0f0a1a7d98ba16429 /lib/errseq.c | |
| parent | x86/ibt,ftrace: Add ENDBR to samples/ftrace (diff) | |
| download | linux-dev-991625f3dd2cbc4b787deb0213e2bcf8fa264b21.tar.xz linux-dev-991625f3dd2cbc4b787deb0213e2bcf8fa264b21.zip | |
x86/ibt: Add IBT feature, MSR and #CP handling
The bits required to make the hardware go.. Of note is that, provided
the syscall entry points are covered with ENDBR, #CP doesn't need to
be an IST because we'll never hit the syscall gap.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Josh Poimboeuf <jpoimboe@redhat.com>
Link: https://lore.kernel.org/r/20220308154318.582331711@infradead.org
Diffstat (limited to 'lib/errseq.c')
0 files changed, 0 insertions, 0 deletions