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| author |   Pratyush Yadav <p.yadav@ti.com> | 2021-05-31 23:47:53 +0530 |
|---|---|---|
| committer |   Tudor Ambarus <tudor.ambarus@microchip.com> | 2021-12-23 15:04:13 +0200 |
| commit | 63017068a6d991fdf31147c4996cd29bfde61ac2 (patch) | |
| tree | df1903952d6b4f8b98ee15921f56945aa09da7b4 /lib/math/git:/ssh: | |
| parent | mtd: spi-nor: core: use 2 data bytes for template ops (diff) | |
| download | linux-dev-63017068a6d991fdf31147c4996cd29bfde61ac2.tar.xz linux-dev-63017068a6d991fdf31147c4996cd29bfde61ac2.zip | |
mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode
The Octal DTR configuration is stored in the CFR5V register. This
register is 1 byte wide. But 1 byte long transactions are not allowed in
8D-8D-8D mode. Since the next byte address does not contain any
register, it is safe to write any value to it. Write a 0 to it.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20210531181757.19458-3-p.yadav@ti.com
Diffstat (limited to 'lib/math/git:/ssh:')
0 files changed, 0 insertions, 0 deletions