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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2021-12-03 11:51:49 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-12-08 10:05:56 +0100 |
| commit | 98ee8b2f66ebff2fafe85668b9d00c3433b76566 (patch) | |
| tree | 64135980167e655a9ff3932c2ed1ffbaedcd64bb /lib/test_overflow.c | |
| parent | clk: renesas: cpg-mssr: Add support for R-Car S4-8 (diff) | |
| download | linux-dev-98ee8b2f66ebff2fafe85668b9d00c3433b76566.tar.xz linux-dev-98ee8b2f66ebff2fafe85668b9d00c3433b76566.zip | |
clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro
Rename the macro CLK_PLL3_DIV4->CLK_PLL3_DIV2_2 to match the clock tree
mentioned in the hardware manual(Rev.1.00 Sep, 2021).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211203115154.31864-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'lib/test_overflow.c')
0 files changed, 0 insertions, 0 deletions