diff options
| author |   Nikola Cornij <nikola.cornij@amd.com> | 2019-06-25 17:19:25 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-07-18 14:27:25 -0500 |
| commit | d68a74541735e030dea56f72746cd26d19986f41 (patch) | |
| tree | 86e5338ef2a5c3c0d279793c73d16980794c81fa /lib/timerqueue.c | |
| parent | drm/amd/display: Optimize gamma calculations (diff) | |
drm/amd/display: Clear FEC_READY shadow register if DPCD write fails
[why]
As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow
register should be cleared and the internal FEC stat should be set to
'not ready'. This is to make sure HW settings will be consistent with
FEC_READY state on the RX.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'lib/timerqueue.c')
0 files changed, 0 insertions, 0 deletions